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page 1 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. the PE43703 is a harp ? -enhanced, high linearity, 7-bit rf digital step attenuator (dsa). this highly versatile dsa covers a 31.75 db attenuation range in 0.25 db, 0.5 db, or 1.0 db steps. the customer can choose which step size and associated specifications are best suited for their application. the peregrine 50 ? rf dsa provides multiple cmos control interfaces and an optional external vss feature. it maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. performance does not change with v dd due to on-board regulator. this next generation peregrine dsa is available in a 5x5 mm 32-lead qfn footprint. the PE43703 is manufactured on peregrine?s ultracmos? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification 50 ? rf digital attenuator 7-bit, 31.75 db, 9 khz - 6000 mhz vss ext option product description figure 2. functional schematic diagram PE43703 features ? harp?-enhanced ultracmos? device ? attenuation options: 0.25 db, 0.5 db, or 1.0 db steps to 31.75 db ? 0.25 db monotonicity for 4.0 ghz ? 0.5 db monotonicity for 5.0 ghz ? 1 db monotonicity for 6.0 ghz ? high linearity: typical +59 dbm iip3 ? excellent low-frequency performance ? optional external vss control (vss ext ) ? 3.3 v or 5.0 v power supply voltage ? fast switch settling time ? programming modes: ? direct parallel ? latched parallel ? serial-addressable: program up to eight addresses 000 - 111 ? high-attenuation state @ power-up (pup) ? cmos compatible ? no dc blocking capacitors required figure 1. package type 32-lead 5x5x0.85 mm qfn package control logic interface rf input rf output switched attenuator array serial in le clk a0 a1 a2 parallel control 7 p/s vss ext (optional)
product specification PE43703 page 2 of 15 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0245-05 ultracmos? rfic solutions -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 atte nuation setting (db) attenuation error (db) 200 mhz 900 mhz 1800 mhz 2200 mhz 3000 mhz 4000 mhz -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 1000 2000 3000 4000 frequency (mhz) attenuation error (db ) 0.25db state 0.5db state 1db state 2db state 4db state 8db state 16db state 31.75db state -0.25 0.00 0.25 0.50 0 4 8 121620242832 attenuation setting (db) step attenuation (db) 200 mhz 900 mhz 1800 mhz 2200 mhz 3000 mhz 5 1015202530 035 5 10 15 20 25 30 0 35 attenuation state attenuation db 0.25-db pe43701 attenuation 900 mhz 1800 mhz 2200 mhz 3000 mhz table 1. electrical specifications: 0.25 db steps @ +25c, v dd = 3.3 v or 5.0 v, vss ext = -2.7 v or gnd notes: 1. please note maximum operating pin (50 ? ) of +23dbm as shown in table 5. 2. to prevent negative voltage generator spurs, supply ?2.7 volts to vss ext . parameter test conditions frequency min typical max units frequency range 9 khz 4000 mhz attenuation range 0.25 db step 0 ? 31.75 db insertion loss 9 khz 4 ghz 1.9 2.4 db attenuation error 0 db - 7.75 db attenuation settings 8 db - 31.75 db attenuation settings 0 db - 31.75 db attenuation settings 9 khz < 3 ghz 9 khz < 3 ghz 3 ghz < 4 ghz ( 0.2+1.5%) (0.15+4%) (0.25+4.5%) db db db return loss 9 khz - 4 ghz 18 db relative phase all states 9 khz - 4 ghz 33 deg p1db (note 1) input 20 mhz - 4 ghz 30 32 dbm iip3 two tones at +18 dbm, 20 mhz spacing 20 mhz - 4 ghz 59 dbm typical spurious value 2 vss ext grounded 1 mhz -110 dbm video feed through 10 mvpp switching time 50% dc ctrl to 10% / 90% rf 650 ns rf trise/tfall 10% / 90% rf 400 ns settling time rf settled to within 0.05 db of final value. rbw = 5 mhz, averaging on. 4 25 s * monotonicity is held so long as step-attenuation does not cross below -0.25 figure 3. 0.25 db step attenuation* performance plots, 0.25 db step figure 4. 0.25 db step, actual vs. ideal attenuation figure 5. 0.25 db major state bit error figure 6. 0.25 db attenuation error ideal attenuation (db) actual attenuation (db)
product specification PE43703 page 3 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. -0.500 0.000 0.500 1.000 0 4 8 121620242832 attenuation setting (db) step attenuation (db) 200 mhz 900 mhz 1800 mhz 2200 mhz 3000 mhz 4000 mhz 5000 mhz 900 mhz 2200 mhz 3800 mhz 5000 mhz 5 1015202530 035 5 10 15 20 25 30 0 35 attenuation state attenuation db 0.5-db PE43703 attenuation table 2. electrical specifications: 0.5 db steps @ +25c, v dd = 3.3 v or 5.0 v, vss ext = -2.7 v or gnd figure 7. 0.5 db step attenuation* performance plots, 0.5 db step parameter test conditions frequency min typical max units frequency range 9 khz 5000 mhz attenuation range 0.5 db step 0 ? 31.5 db insertion loss 9 khz 5 ghz 2.0 2.6 db attenuation error 0 db - 31.5 db attenuation settings 0 db - 16.5 db attenuation settings 17 db - 31.5 db attenuation settings 9 khz < 4 ghz 4 5 ghz 4 5 ghz (0.25+4.5%) (0.3+5%) (1.3+0%) db db db return loss 9 khz - 5 ghz 18 db relative phase all states 9 khz - 5 ghz 56 deg p1db (note 1) input 20 mhz - 5 ghz 30 32 dbm iip3 two tones at +18 dbm, 20 mhz spacing 20 mhz - 5 ghz 57 dbm typical spurious value 2 vss ext grounded 1 mhz -110 dbm video feed through 10 mvpp switching time 50% dc ctrl to 10% / 90% rf 650 ns rf trise/tfall 10% / 90% rf 400 ns settling time rf settled to within 0.05 db of final value. rbw = 5 mhz, averaging on. 4 25 s *monotonicity is held so long as step-attenuation does not cross below -0.5 figure 8. 0.5 db step, actual vs. ideal attenuation figure 9. 0.5 db major state bit error figure 10. 0.5 db attenuation error ideal attenuation (db) actual attenuation (db) -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 1000 2000 3000 4000 5000 frequency (mhz) attenuation error (db) 0.5db state 1db state 2db state 4db state 8db state 16db stat e 31.5db st ate -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 attenuation setting (db) attenuation error (db) 200 mhz 900 mhz 1800 mhz 2200 mhz 3000 mhz 4000 mhz 5000 mhz notes: 1. please note maximum operating pin (50 ? ) of +23dbm as shown in table 5. 2. to prevent negative voltage generator spurs, supply ?2.7 volts to vss ext .
product specification PE43703 page 4 of 15 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0245-05 ultracmos? rfic solutions -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 4 8 121620242832 attenuation setting (db) attenuation error (db ) 200 mhz 900 mhz 1800 mhz 2200 mhz -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 1000 2000 3000 4000 5000 6000 frequency (mhz) bit error (db) 1db state 2db state 4db state 8db state 16db state 31db state -1 -0.5 0 0.5 1 0 4 8 12 16 20 24 28 32 attenuation setting (db) step attenuation (db) 200 mhz 900 mhz 1800 mhz 2200 mhz 3000 mhz 4000 mhz 5000 mhz 6000 mhz 900 mhz 2200 mhz 3800 mhz 5800 mhz 5 1015202530 035 5 10 15 20 25 30 0 35 attenuation state attenuation db 1-db PE43703 attenuation table 3. electrical specifications: 1 db steps @ +25c, v dd = 3.3 v or 5.0 v, vss ext = -2.7 v or gnd performance plots, 1 db step parameter test conditions frequency min typical max units frequency range 9 khz 6000 mhz attenuation range 1 db step 0 - 31 db insertion loss 9 khz 6 ghz 2.3 2.8 db attenuation error 0 db - 31 db attenuation settings 0 db - 12 db attenuation settings 13 db - 31 db attenuation setting 0 db - 31 db attenuation settings 9 khz ? 4 ghz 4 ghz 6 ghz 4 ghz 6 ghz 4 ghz 6 ghz (0.25+4.5%) +0.4+8% +1.4+0% -0.2-3% db db db db return loss 9 khz - 6 ghz 18 db relative phase all states 9 khz - 6 ghz 74 deg p1db (note 1) input 20 mhz - 6 ghz 30 32 dbm iip3 two tones at +18 dbm, 20 mhz spacing 20 mhz - 6 ghz 53 dbm typical spurious value 2 vss ext grounded 1 mhz -110 dbm video feed through 10 mvpp switching time 50% dc ctrl to 10% / 90% rf 650 ns rf trise/tfall 10% / 90% rf 400 ns settling time rf settled to within 0.05 db of final value. rbw = 5 mhz, averaging on. 4 25 s *monotonicity is held so long as step-attenuation not cross below -1 figure 12. 1 db step, actual vs. ideal attenuation figure 11. 1 db step attenuation figure 13. 1 db major state bit error figure 14. 1 db attenuation error ideal attenuation (db) actual attenuation (db) notes: 1. please note maximum operating pin (50 ? ) of +23dbm as shown in table 5. 2. to prevent negative voltage generator spurs, supply ?2.7 volts to vss ext .
product specification PE43703 page 5 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0123456789 frequency (ghz) return loss (db) -40c 25c 85c -40 -35 -30 -25 -20 -15 -10 -5 0 0123456789 frequency (ghz) return loss (db) -40c 25c 85c -60 -50 -40 -30 -20 -10 0 0123456789 frequency (ghz) return loss (db) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 frequency (ghz) insertion loss (db) -40c +25c +85c -70 -60 -50 -40 -30 -20 -10 0 0123456789 frequency (ghz) return loss (db) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 4 8 121620242832 attenuation setting (db) attenuation error (db) 3000 mhz 4000 mhz 5000 mhz 6000 mh z figure 15. 1 db attenuation error (continued) figure 16. insertion loss @ temperature performance plots, 1 db step (continued) figure 17. input return loss (+25c) figure 18. output return loss (+25c) figure 19. input return loss @ temperature for 16 db state figure 20. output return loss @ temperature for 16 db state
product specification PE43703 page 6 of 15 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0245-05 ultracmos? rfic solutions 30 35 40 45 50 55 60 65 70 0 1000 2000 3000 4000 5000 6000 7000 frequency (mhz) input ip3 (dbm) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 4 8 121620242832 attenuation setting (db) attenuation error (db) +25c -40c +85c -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 4 8 121620242832 attenuation setting (db) attenuation error (db) +25c -40c +85c -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 attenuation setting (db) attenuation error (db) +25 c -40c +85c 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 -40 -20 0 20 40 60 80 temperature (deg c) phase (deg) 900 mhz 1800 mhz 3000 mhz 0 20 40 60 80 100 120 012345678 frequency (ghz) relative phase error (deg) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db figure 21. relative phase error figure 22. relative phase error vs. temperature for 31.75 db state performance plots (continued) figure 23. attenuation error @ 900 mhz figure 24. attenuation error @ 1800 mhz figure 25. attenuation error @ 3000 mhz figure 26. input ip3 vs. frequency
product specification PE43703 page 7 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. exposed solder pad connection the exposed solder pad on the bottom of the package must be grounded for proper device operation. figure 27. pin configuration (top view) latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. switching frequency the PE43703 has a maximum 25 khz switching rate when vss ext is grounded. switching rate is defined to be the speed at which the dsa can be toggled across attenuation states. pin no. pin name description 1 n/c no connect 2 v dd power supply pin 3 p ? /s serial/parallel mode select 4 a0 address bit a0 connection 5 gnd ground 6 gnd ground 7 rf1 rf1 port 8 - 17 gnd ground 18 rf2 rf2 port 19 gnd ground 20 vss ext external vss control 21 a2 address bit a2 connection 22 a1 address bit a1 connection 23 le serial interface latch enable input 24 clk serial interface clock input 25 si serial interface data input 26 c16 (d6) parallel control bit, 16 db 27 c8 (d5) parallel control bit, 8 db 28 c4 (d4) parallel control bit, 4 db 29 c2 (d3) parallel control bit, 2 db 30 c1 (d2) parallel control bit, 1 db 31 c0.5 (d1) parallel control bit, 0.5 db 32 c0.25 (d0) parallel control bit, 0.25 db paddle gnd ground for proper operation 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 16 15 14 13 12 11 10 9 exposed solder pad nc v dd p/s a0 gnd gnd rf1 gnd gnd gnd gnd gnd gnd gnd gnd gnd clk le a1 a2 vss ext gnd rf2 gnd c0.25 c0.5 c1 c2 c4 c8 c16 si optional external vss control ( vss ext ) for proper operation, the vss ext control must be grounded or at the vss voltage specified in the operating ranges table. when the vss ext control pin on the package is grounded the switch fet?s are biased with an internal low spur negative voltage generator. for applications that require the lowest possible spur performance, vss ext can be applied to bypass the internal negative voltage generator to eliminate the spurs. table 4. pin descriptions moisture sensitivity level the moisture sensitivity level rating for the PE43703 in the 5x5 qfn package is msl1. note: ground c0.25, c0.5, c1 c2, c4, c8, c16 if not in use.
product specification PE43703 page 8 of 15 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0245-05 ultracmos? rfic solutions 0.0 5.0 10.0 15.0 20.0 25.0 30.0 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 1.0e+09 hz pin dbm note: 1. applied only when external vss power supply used. pin 20 must be grounded when using internal vss supply table 5. operating ranges table 6. absolute maximum ratings parameter min typ max units v dd 3.3 v power supply voltage 3.0 3.3 3.6 v v dd 5.0 v power supply voltage 4.5 5.0 5.5 v vss ext negative power supply voltage 1 -3.0 -2.7 -2.4 v i dd power supply current 70 350 a digital input high 2.6 5.5 v p in input power (50 ? ): 9 khz 20 mhz 20 mhz 6 ghz see fig. 28 +23 dbm dbm t op operating temperature range -40 25 85 c digital input low 0 1 v digital input leakage 15 a symbol parameter/conditions min max units v dd power supply voltage -0.3 6.0 v vss ext vss external negative power supply voltage (optional) -4.0 0.3 v v i voltage on any digital input -0.3 5.8 v t st storage temperature range -65 150 c v esd esd voltage (hbm) 1 esd voltage (machine model) 500 100 v v p in input power (50 ? ) 9 khz 20 mhz 20 mhz 6 ghz see fig. 28 +23 dbm dbm figure 28. maximum power handling capability: z 0 = 50 ? exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. note: 1. human body model (hbm, mil_std 883 method 3015.7)
product specification PE43703 page 9 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. table 8. latch and clock specifications latch enable function 0 shift register clocked contents of shift register transferred to attenuator core shift clock x attenuation word d7 d6 d5 d4 d3 d2 d1 d0 (lsb) l l l l l l l l reference i.l. l l l l l l l h 0.25 db l l l l l h l l 1 db l l l l h l l l 2 db l l l h l l l l 4 db l l h l l l l l 8 db l h l l l l l l 16 db l h h h h h h h 31.75 db attenuation setting rf1-rf2 l l l l l l h l 0.5 db table 11. serial attenuation word truth table address word address setting a7 (msb) a6 a5 a4 a3 a2 a1 a0 x x x x x l l l 000 x x x x x l l h 001 x x x x x l h l 010 x x x x x l h h 011 x x x x x h l l 100 x x x x x h l h 101 x x x x x h h l 110 x x x x x h h h 111 table 10. serial address word truth table table 7. control voltage state bias condition low 0 to +1.0 vdc at 2 a (typ) high +2.6 to +5 vdc at 10 a (typ) parallel control setting attenuation setting rf1-rf2 d6 d5 d4 d3 d2 d1 d0 l l l l l l l reference i.l. l l l l l l h 0.25 db l l l l l h l 0.5 db l l l l h l l 1 db l l l h l l l 2 db l l h l l l l 4 db l h l l l l l 8 db h l l l l l l 16 db h h h h h h h 31.75 db table 9. parallel truth table table 12. serial-addressable register map q15 q14 q13 q12 q11 q10 a7 a6 a5 a4 a3 a2 q9 q8 q7 q6 q5 q4 a1 a0 d7 d6 d5 d4 q3 q2 q1 q0 d3 d2 d1 d0 address word attenuation word lsb (first in) msb (last in) bits can either be set to logic high or logic low attenuation word is derived directly from the attenuation value. for example, to program the 18.25 db state at address 3: address word: xxxxx011 attenuation word: multiply by 4 and convert to binary 4 * 18.25 db 73 01001001 serial input: xxxxx01101001001 d7 must be set to logic low
product specification PE43703 page 10 of 15 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0245-05 ultracmos? rfic solutions programming options parallel/serial selection either a parallel or serial-addressable interface can be used to control the PE43703. the p ? /s bit provides this selection, with p ? /s=low selecting the parallel interface and p ? /s=high selecting the serial- addressable interface. parallel mode interface the parallel interface consists of seven cmos- compatible control lines that select the desired attenuation state, as shown in table 9 . the parallel interface timing requirements are defined by fig. 30 (parallel interface timing diagram), table 9 (parallel interface ac characteristics), and switching speed ( table 1 ). for latched -parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low ( per fig. 30 ) to latch new attenuation state into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will c hange device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). serial-addressable interface the serial-addressable interface is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. the 16-bits make up two words comprised of 8-bits each. the first word is the attenuation word, which controls the state of the dsa. the second word is the address word, which is compared to the static (or programmed) logical states of the a0, a1 and a2 digital inputs. if there is an address match, the dsa changes state; otherwise its current state will remain unchan ged. fig. 29 illustrates an example timing diagram for programming a state. it is required that all parallel control inputs be grounded when the dsa is used in serial- addressable mode. the serial-addressable interface is controlled using three cmos-compatible signals: serial-in (si), clock (clk), and latch enable (le). the si and clk inputs allow data to be serially entered into the shift register. serial data is clocked in lsb first, beginning with the attenuation word. the shift register must be loaded while le is held low to prevent the attenuator value from changing as data is entered. the le input should then be toggled high and brought low again, latching the new data into the dsa. address word and attenuation word truth tables are listed in table 10 & table 11 , respectively. a programming example of the serial-addressable register is illustrated in table 12 . the serial-addressable timing diagram is illustrated in fig. 29. power-up control settings the PE43703 will always initialize to the maximum attenuation setting (31.75 db) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. in direct- parallel mode, the dsa can be preset to any state within the 31.75 db range by pre-setting the parallel control pins prior to power-up. in this mode, there is a 400- s delay between the time the dsa is powered-up to the time the desired state is set. during this power-up delay, the device attenuates to the maximum attenuation setting (31.75 db) before defaulting to the user defined state. if the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). dynamic operation between serial-addressable and parallel programming modes is possible. if the dsa powers up in serial-addressable mode (p/ s = high), all the parallel control inputs di[6:0] must be set to logic low. prior to toggling to parallel mode, the dsa must be programmed serially to ensure d[7] is set to logic low. if the dsa powers up in either latched or direct- parallel mode, all parallel pins di[6:0] must be set to logic low prior to toggling to serial-addressable mode ( p ? /s = high), and held low until the dsa has been programmed serially to ensure bit d[7] is set to logic low. the sequencing is only required once on power- up. once completed, the dsa may be toggled between serial-addressable and parallel programming modes at will.
product specification PE43703 page 11 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. v dd = 3.3 or 5.0 v, -40 c < t a < 85 c, unless otherwise specified v dd = 3.3 or 5.0 v, -40 c < t a < 85 c, unless otherwise specified figure 29. serial-addressable timing diagram figure 30. latched-parallel/direct-parallel timing diagram symbol parameter min max unit f clk serial clock frequency - 10 mhz t clkh serial clock high time 30 - ns t clkl serial clock low time 30 - ns t lesu last serial clock rising edge setup time to latch enable rising edge 10 - ns t lepw latch enable min. pulse width 30 - ns t sisu serial data setup time 10 - ns t sih serial data hold time 10 - ns t disu parallel data setup time 100 - ns t dih parallel data hold time 100 - ns t asu address setup time 100 - ns t ah address hold time 100 - ns t pssu parallel/serial setup time 100 - ns t psh parallel/serial hold time 100 - ns t pd digital register delay (internal) - 10 ns symbol parameter min max unit t lepw latch enable minimum pulse width 30 - ns t disu parallel data setup time 100 - ns t dih parallel data hold time 100 - ns t pssu parallel/serial setup time 100 - ns t psih parallel/serial hold time 100 - ns t pd digital register delay (internal) - 10 ns t dipd digital register delay (internal, direct mode only) - 5 ns valid t disu t dih di[6:0] le p/s t pssu t psh t lepw valid do[6:0] t dipd t pd table 14. parallel and direct interface ac characteristics table 13. serial-addressable interface ac characteristics a[2] a[1] a[0] t sisu t clkl t lepw t sih t clkh si clk le p/s t lesu t pssu t psih valid t asu add[2:0] t ai h do[6:0] valid di[6:0] t pd t disu t dih d[6] d[5] d[4] d[3] d[2] d[1] d[0] d[7] d[7] must be set to logic low bits can either be set to logic high or logic low
product specification PE43703 page 12 of 15 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0245-05 ultracmos? rfic solutions evaluation kit the digital attenuator evaluation kit board was designed to ease customer evaluation of the PE43703 digital step attenuator. direct-parallel programming procedure for automated direct-parallel programming, connect the test harness provided with the evk from the parallel port of the pc to the j1 & serial header pin and set the d0-d6 sp3t switches to the ?middle? toggle position. position the parallel/ serial ( p ? /s) select switch to the parallel (or left) position. the evaluation software is written to operate the dsa in either parallel or serial- addressable mode. ensure that the software is set to program in direct-parallel mode. using the software, enable or disable each setting to the desired attenuation state. the software automatically programs the dsa each time an attenuation state is enabled or disabled. for manual direct-parallel programming, disconnect the test harness provided with the evk from the j1 and serial header pins. position the parallel/serial ( p ? /s) select switch to the parallel (or left) position. the le pin on the serial header must be tied to v dd . switches d0-d6 are sp3t switches which enable the user to manually program the parallel bits. when any input d0-d6 is toggled ?up?, logic high is presented to the parallel input. when toggled ?down?, logic low is presented to the parallel input. setting d0-d6 to the ?middle? toggle position presents an open, which forces an on-chip logic low. table 9 depicts the parallel programming truth table and fig. 30 illustrates the parallel programming timing diagram. latched-parallel programming procedure for automated latched-parallel programming, the procedure is identical to the direct-parallel method. the user only must ensure that latched-parallel is selected in the software. for manual latched-parallel programming, the procedure is identical to direct-parallel except now the le pin on the serial header must be logic low as the parallel bits are applied. the user must then pulse le from 0v to v dd and back to 0v to latch the programming word into the dsa. le must be logic low prior to programming the next word. figure 31. evaluation board layout peregrine specification 101-0312 serial-addressable programming procedure position the parallel/serial ( p ? /s) select switch to the serial (or right) position. prior to programming, the user must define an address setting using the add header pin. jump the middle pins on the add header a0-a2 (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. if the add pins are left open, then 000 become the default address. the evaluation software is written to operate the dsa in either parallel or serial-addressable mode. ensure that the software is set to program in serial-addressable mode. using the software, enable or disable each setting to the desired attenuation state. the software automatically programs the dsa each time an attenuation state is enabled or disabled. note: reference fig. 32 for evaluation board schematic
product specification PE43703 page 13 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. figure 33. package drawing qfn 5x5 mm a max 0.900 nom 0.850 min 0.800 figure 32. evaluation board schematic peregrine specification 102-0381 note: capacitors c1-c8, c13, & c14 may be omitted.
product specification PE43703 page 14 of 15 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0245-05 ultracmos? rfic solutions table 15. ordering information figure 34. tape and reel drawing order code part marking description package shipping method PE43703mli 43703 PE43703 g - 32qfn 5x5mm-75a green 32-lead 5x5mm qfn bulk or tape cut from reel PE43703mli-z 43703 PE43703 g ? 32qfn 5x5mm-3000c green 32-lead 5x5mm qfn 3000 units / t&r ek43703-01 43703 PE43703 g ? 32qfn 5x5mm-ek evaluation kit 1 / box figure 35. marking specifications 43703 yyww zzzzz yyww = date code zzzzz = last five digits of lot number device orientation in tape top of device pin 1 tape feed direction
product specification PE43703 page 15 of 15 document no. 70-0245-05 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liabilit y for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. high-reliability and defense products americas san diego, ca, usa phone: 858-731-9475 fax: 848-731-9499 europe/asia-pacific aix-en-provence cedex 3, france phone: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213

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